1. Field of the Invention
The present invention relates to the fabrication of integrated circuit devices on semiconductor substrates and, more particularly relates to methods and structures for critical dimension (CD) or profile measurement.
2. Description of the Related Art
The Complementary Metal Oxide Semiconductor (CMOS) technology has been recognized as the leading technology for use in digital electronics in general and for use in many computer products in particular. The miniaturization of CMOS technology according to a scaling rule is used in a semiconductor device to achieve large-scale integration and high-speed operation. Due to minimization of integrated circuits, control of dimensions of devices becomes more important. In order to precisely control the dimensions of the devices, measurement for control dimension (CD) has been paid more attention during the process of manufacturing integrated circuits.
FIG. 1A shows a prior art method for measuring critical dimension of (CD) of a structure. The prior art method first provides a substrate 100a with periodic trenches 110a therein. A scatterometry optical critical dimension (OCD) method is used to measure the dimension of the trenches 110a. Light beams 120a arrive at the periodic trenches 110a and reflects so as to create a scattering spectrum. According to the scattering spectrum, the dimension of the trenches 110a can be measured.
FIG. 1B shows a prior art method for measuring critical dimension of (CD) of another structure. The prior art method also provides a substrate 100b with periodic trenches 110b therein. Spacers 115 are formed on the sidewalls of the trenches 110b. A scatterometry optical critical dimension (OCD) method is used to measure the dimension of the trenches 110b and the spacers 115. Light beams 120b arrive at the periodic trenches 110b and reflects so as to create a scattering spectrum. According to the scattering spectrum, the dimension of the trenches 110b and the spacers 115 can be measured.
These prior art methods described above use a non-planarized grating structure for Scatterometry OCD measurement.
U.S. Patent Application No. 2004/0058460 A1 discloses scatterometry test structures stacked over same footprint area. The prior art describes a plurality of scatterometry test structures for use in process control during fabrication of a semiconductor wafer having multilevel integrated circuit chips. Many of said levels have a feature size of a critical dimension. The scatterometry test structures on the wafer are at each level, suitable to measure critical dimensions. The second level and each subsequent level of the test structures are located to fit into the same footprint area as the first level. This prior art method also uses a non-planarized grating structure for Scatterometry OCD measurement. After Scatterometry OCD measurement, the periodic pattern is planarized with a dielectric layer.
Accordingly, methods and structures for CD or profile measurement are desired in this industry.